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<title>MULSS—Multiply Scalar Single-Precision Floating-Point Values </title></head>
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<h1>MULSS—Multiply Scalar Single-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>F3 0F 59 /r</p>
<p>MULSS xmm1,xmm2/m32</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE</td>
<td>Multiply the low single-precision floating-point value in xmm2/m32 by the low single-precision floating-point value in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.F3.0F.WIG 59 /r</p>
<p>VMULSS xmm1,xmm2, xmm3/m32</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Multiply the low single-precision floating-point value in xmm3/m32 by the low single-precision floating-point value in xmm2.</td></tr>
<tr>
<td>
<p>EVEX.NDS.LIG.F3.0F.W0 59 /r</p>
<p>VMULSS xmm1 {k1}{z}, xmm2, xmm3/m32 {er}</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply the low single-precision floating-point value in xmm3/m32 by the low single-precision floating-point value in xmm2.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>T1S</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Multiplies the low single-precision floating-point value from the second source operand by the low single-precision floating-point value in the first source operand, and stores the single-precision floating-point result in the destina-tion operand. The second source operand can be an XMM register or a 32-bit memory location. The first source operand and the destination operands are XMM registers.</p>
<p>128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-1:32) of the corresponding YMM destination register remain unchanged.</p>
<p>VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order doublewords of the destination operand are copied from the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.</p>
<p>EVEX encoded version: The low doubleword element of the destination operand is updated according to the writemask.</p>
<p>Software should ensure VMULSS is encoded with VEX.L=0. Encoding VMULSS with VEX.L=1 may encounter unpre-dictable behavior across different processor generations.</p>
<p><strong>Operation</strong></p>
<p><strong>VMULSS (EVEX encoded version)</strong></p>
<p>IF (EVEX.b = 1) AND SRC2 *is a register*</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>IF k1[0] or *no writemask*</p>
<p>THEN</p>
<p>DEST[31:0] (cid:197) SRC1[31:0] * SRC2[31:0]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[31:0] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>THEN DEST[31:0] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[127:32] (cid:197) SRC1[127:32]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>VMULSS (VEX.128 encoded version)</strong></p>
<p>DEST[31:0] (cid:197)SRC1[31:0] * SRC2[31:0]</p>
<p>DEST[127:32] (cid:197)SRC1[127:32]</p>
<p>DEST[MAX_VL-1:128] (cid:197)0</p>
<p><strong>MULSS (128-bit Legacy SSE version)</strong></p>
<p>DEST[31:0] (cid:197)DEST[31:0] * SRC[31:0]</p>
<p>DEST[MAX_VL-1:32] (Unmodified)</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VMULSS __m128 _mm_mask_mul_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);</p>
<p>VMULSS __m128 _mm_maskz_mul_ss( __mmask8 k, __m128 a, __m128 b);</p>
<p>VMULSS __m128 _mm_mul_round_ss( __m128 a, __m128 b, int);</p>
<p>VMULSS __m128 _mm_mask_mul_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);</p>
<p>VMULSS __m128 _mm_maskz_mul_round_ss( __mmask8 k, __m128 a, __m128 b, int);</p>
<p>MULSS __m128 _mm_mul_ss(__m128 a, __m128 b)</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Underflow, Overflow, Invalid, Precision, Denormal</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 3.</p>
<p>EVEX-encoded instruction, see Exceptions Type E3.</p></body></html>